The present invention relates to a system for storing and retrieving digital information, and more particularly to a system for compressing the amount of digital information that is stored in a local data channel memory for a digital tester to thereby decrease the amount of storage space required to provide for a thorough exercising of an electronic component.
In a digital tester such as an in-circuit/functional electronic component tester of the type disclosed in U.S. Pat. No. 3,870,953, test vectors are generated in a central control computer and eventually applied to various nodes on a printed circuit board to cause an electronic component on the board, such as an integrated circuit chip, to produce response signals at other nodes. The response signals produced by the component under test are compared with expected responses to determine whether the component is functioning properly. The nature of the test vectors that are applied to the nodes as stimulus signals is such that they do not harm other components on the circuit board but they drive the node of the circuit under test sufficiently to overcome the influence of other components that might be connected to that node. In other digital testers for testing electronic components that are not connected to other circuits, e.g. individual IC's, or for functionally testing entire circuit boards through edge connectors, stimulus signals are similarly applied and responses are similarly measured, but the problems of harming other components and overcoming other signal levels are not present.
A typical digital tester might have over 500 individual data channels through which stimulus signals are applied to the circuit board and response signals are received. In order to increase the rate at which the test vectors are applied to the circuit board, each data channel has its own local memory that is loaded with the test vectors generated in the central computer at the initiation of a test procedure. The local memories can apply the test vectors to the circuit board at a much faster rate than they can be generated by the computer, as well as independently of one another, to thereby substantially decrease the time it takes to thoroughly exercise all of the electronic components on the circuit board.
As the state of microelectronics advances and integrated circuits evolve from small scale to large scale and very large scale devices, the length of a test pattern, i.e., the number of test vectors, required to thoroughly check a component increases substantially, and taxes the limits of the local memory for each data channel. This problem is particularly acute in testers which utilize shift registers to implement the local memory for each data channel. Once the contents of the memory has been shifted out of the registers, it must be reloaded with new test vectors before the test procedure can resume. The time it takes to load information into a local memory plays a significant role in the overall rate at which a device can be tested, and hence the need to reload during a test substantially reduces the total efficiency of the test procedure. In addition, another problem associated with the shift register type memories is the fact that once a test vector is shifted out of the memory, it cannot be reused until it has been reloaded into the memory and shifted through all of its stages.
In an effort to overcome the problems associated with shift register type memories, other testers utilize random access (RAM) type memories to store the data channel information. This implementation allows the test vectors to be applied to the nodes on the circuit board by addressing predetermined locations within the memory, and hence allows test vectors to be reused since they are not "lost" when they are read out of the memory. In addition, random access memories enable subroutines and looping instructions to be utilized to recall stored test vectors, so that it is not necessary to allocate one memory location for each cycle in the test procedure, thereby providing a measure of test data compression. However, one drawback associated with prior art random access type memories is the fact that they are not capable of accessing variable data when executing a sequence in the test procedure. In other words, once the test vectors are loaded from the central control computer into the RAMs, the data is fixed and the sequence of test vectors cannot be modified in response to different types of output signals from the circuit being tested.
One type of memory system that attempts to overcome this problem is disclosed in an article entitled "Compressing Test Patterns To Fit Into LSI Testers" by Trent Cave, Electronics Magazine, Oct. 12, 1978, pages 136-140. The local memory system disclosed therein utilizes both a random access memory and a shift register to store the test vectors for the data channel. Test pattern vectors are loaded into the RAM and are addressed with a test pattern controller. The shift register is loaded with variable data that can be inserted into the test pattern, for example between subroutines or loops executed with the RAM, in a first-in, first-out manner.
Although this dual memory approach enables variable data to be inserted into a test pattern stored within a random access memory, it still suffers from the drawbacks associated with shift register memories. Specifically, once a variable in the test vector has been shifted out of the shift register memory, it cannot be reused until it has been reloaded into the memory. The need to reload the shift register each time a new variable is to be inserted into the test pattern continues to play a significant role in the overall throughput capabilities of the tester.
Accordingly, it is a general object of the present invention to provide a novel system for compressing test vector information stored in the local memory of a digital tester.
It is another object of the present invention to provide a novel data channel memory system that does not require the use of shift registers to insert variables into the test pattern.
It is yet another object of the present invention to provide a novel local memory system that allows a test vector variable to be reused without having to restore it prior to each reuse thereof.
It is a further object of the present invention to utilize a random access type memory to store both fixed and variable test vectors, and to provide a source of address information for accessing the variables stored in the memory when they are required to be inserted in a test pattern.